A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution

Yuandong Li, Li Du, Yuan Du. A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution. In 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2023, Hangzhou, China, June 11-13, 2023. pages 1-5, IEEE, 2023. [doi]

Abstract

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