Tun Li, Yang Guo, Sikun Li, Fujiang Ao, GongJie Li. Parallel verilog simulation: architecture and circuit partition. In Masaharu Imai, editor, Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004. pages 644-646, IEEE, 2004. [doi]
@inproceedings{LiGLAL04,
title = {Parallel verilog simulation: architecture and circuit partition},
author = {Tun Li and Yang Guo and Sikun Li and Fujiang Ao and GongJie Li},
year = {2004},
doi = {10.1145/1015090.1015265},
url = {http://doi.acm.org/10.1145/1015090.1015265},
tags = {architecture, partitioning},
researchr = {https://researchr.org/publication/LiGLAL04},
cites = {0},
citedby = {0},
pages = {644-646},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004},
editor = {Masaharu Imai},
publisher = {IEEE},
isbn = {0-7803-8175-0},
}