Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS - researchr publication authors

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Junshang Li, Zishang He, Yajie Qin. Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS. In 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. pages 1-4, IEEE, 2019. [doi]

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