Kai Li, Mitsuyoshi Ito, Atsushi Esumi. A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined scheme. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, September 22-25, 2013. pages 1-3, IEEE, 2013. [doi]
Abstract is missing.