Xin Li, Wulong Liu, Haixiao Du, Yu Wang 0002, Yuchun Ma, Huazhong Yang. Whitespace-aware TSV arrangement in 3D clock tree synthesis. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013. pages 115-120, IEEE, 2013. [doi]
Abstract is missing.