Jun Li, Ying Liang, Shengkai Wang, Jun Yang. Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA. In EITCE 2020: 4th International Conference on Electronic Information Technology and Computer Engineering, Xiamen, China, 6 November, 2020 - 8 November, 2020. pages 658-662, ACM, 2020. [doi]
Abstract is missing.