An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS

Dengquan Li, Maliang Liu, Lei Zhao, Henghui Mao, Ruixue Ding, Zhangming Zhu. An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS. IEEE Trans. on Circuits and Systems, 67-II(11):2307-2311, 2020. [doi]

@article{LiLZMDZ20,
  title = {An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS},
  author = {Dengquan Li and Maliang Liu and Lei Zhao and Henghui Mao and Ruixue Ding and Zhangming Zhu},
  year = {2020},
  doi = {10.1109/TCSII.2020.2968457},
  url = {https://doi.org/10.1109/TCSII.2020.2968457},
  researchr = {https://researchr.org/publication/LiLZMDZ20},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {67-II},
  number = {11},
  pages = {2307-2311},
}