Xi Li, Min Pan, Tong Liu, Peter A. Beerel. Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022. pages 62-67, IEEE, 2022. [doi]
@inproceedings{LiPLB22,
title = {Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic},
author = {Xi Li and Min Pan and Tong Liu and Peter A. Beerel},
year = {2022},
doi = {10.1109/ISVLSI54635.2022.00024},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00024},
researchr = {https://researchr.org/publication/LiPLB22},
cites = {0},
citedby = {0},
pages = {62-67},
booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022},
publisher = {IEEE},
isbn = {978-1-6654-6605-9},
}