Abstract is missing.
- HAJPAQUE: Hardware Accelerator for JSON Parsing, Querying and Schema ValidationSamiksha Agarwal, Smruti R. Sarangi. 1-7 [doi]
- Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate AddersShalini Singh, Pavan Kumar Pothula, Madhav Rao. 8-13 [doi]
- Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural NetworksAlessio Carpegna, Alessandro Savino, Stefano Di Carlo. 14-19 [doi]
- A Methodology for Identifying Critical Sequential Circuits with Graph Convolutional NetworksLi Lu, Junchao Chen, Markus Ulbricht 0002, Milos Krstic. 20-25 [doi]
- Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUsJosie E. Rodriguez Condia, Riccardo Faggiano, Matteo Sonza Reorda. 26-31 [doi]
- High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional TestAdeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar. 32-37 [doi]
- An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer PrincipleLucas Klemmer, Daniel Große. 38-43 [doi]
- Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing ClustersGianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini. 44-49 [doi]
- MIDAS: Mutual Information Driven Approximate SynthesisSina Boroumand, Christos-Savvas Bouganis, George A. Constantinides. 50-55 [doi]
- Processing-in-Memory with Temporal EncodingMohammad Nazmus Sakib, Rahul Sreekumar, Xinyuan Zhu, Tommy Tracy II, Mircea R. Stan. 56-61 [doi]
- Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive LogicXi Li, Min Pan, Tong Liu, Peter A. Beerel. 62-67 [doi]
- Variation-aware Design Space Exploration of Mott Memristor-based NeuristorsShamiul Alam, Md. Mazharul Islam 0006, Akhilesh Jaiswal, Nathaniel C. Cady, Garrett S. Rose, Ahmedullah Aziz. 68-73 [doi]
- A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address TranslationKyle Kuan, Tosiron Adegbija. 74-79 [doi]
- Deriving FSM-based tests using $a, b-\text{faults}$ for Logic CircuitsAndrey Laputenko, Nina Yevtushenko 0001, Valentina Andreeva, Anzhela Yu. Matrosova. 80-85 [doi]
- Optimization of BDD-based Approximation Error Metrics CalculationsVojtech Mrazek. 86-91 [doi]
- Polynomial Formal Verification of Approximate FunctionsMartha Schnieber, Saman Fröhlich, Rolf Drechsler. 92-97 [doi]
- RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon PhotonicsFebin Sunny, Mahdi Nikdast, Sudeep Pasricha. 98-103 [doi]
- Automated Mapping of Asynchronous Circuits on FPGA under Timing ConstraintsGang Mao, Alex Yakovlev, Fei Xia, Shengqi Yu, Rishad A. Shafik. 104-109 [doi]
- An Efficient Accelerator of Deformable 3D Convolutional Network for Video Super-ResolutionSiyu Zhang, Wendong Mao, Zhongfeng Wang. 110-115 [doi]
- Adaptable Multi-level Voltage to Binary Converter Using Ferroelectric FETsSanjay Das, Arun Govindankutty, Shan Deng, Kai Ni 0004, Sumitha George. 116-121 [doi]
- Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing SystemsJun Feng 0008, Shixi Chen, Jiaxu Zhang, Yuxiang Fu, Jiang Xu 0001. 122-127 [doi]
- Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket HypothesisSanmitra Banerjee, Mahdi Nikdast, Sudeep Pasricha, Krishnendu Chakrabarty. 128-133 [doi]
- LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault AnalysisAmit Mazumder Shuvo, Nitin Pundir, Jungmin Park, Farimah Farahmandi, Mark M. Tehranipoor. 134-139 [doi]
- ISPLock: A Hybrid Internal State Locking Method Using Polymorphic GatesNikhil Saxena, Ranga Vemuri. 140-145 [doi]
- On Protecting IJTAG from Data Sniffing and Alteration AttacksAnjum Riaz, Gaurav Kumar, Jaynarayan T. Tudu, Satyadev Ahlawat. 146-151 [doi]
- TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNsHarideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen. 152-157 [doi]
- Performance Evaluation of Video Analytics Workloads on Emerging Processing-In-Memory ArchitecturesNagadastagiri Challapalle, Vijaykrishnan Narayanan. 158-163 [doi]
- Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement LearningXiao Li, Lin Chen, Shixi Chen, Fan Jiang, Chengeng Li, Jiang Xu 0001. 164-169 [doi]
- zk -Sherlock: Exposing Hardware Trojans in Zero-KnowledgeDimitris Mouris, Charles Gouert, Nektarios Georgios Tsoutsos. 170-175 [doi]
- LOKI: A Hardware Trojan Affecting Multiple Components of an SoCManju Rajan, Abhijit Das 0002, John Jose. 176-181 [doi]
- Enhancing Security of Memristor Computing System Through Secure Weight MappingMinhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang 0209, Shahar Kvatinsky. 182-187 [doi]
- Delay-aware evolutionary optimization of digital circuitsJitka Kocnová, Zdenek Vasícek. 188-193 [doi]
- CmpctArch: A Generic Low Power Architecture for Compact Data Structures in Energy Harvesting DevicesPriyanka Singla 0001, Smruti R. Sarangi. 194-199 [doi]
- LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable StrideDionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 200-205 [doi]
- High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication SystemsKumari Suravi, Rahul Shrestha. 206-211 [doi]
- An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s NetworkingLei Yang, Jing Tian 0004, Bo Wu, Zhongfeng Wang, Hao Ren. 212-216 [doi]
- A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOIMattis Hasler, Sebastian Haas, Robert Wittig, Stefan Scholze, Andreas Dixius, Sebastian Höppner, Gerhard P. Fettweis, Christian Mayr 0001. 217-222 [doi]
- Improving GPU Throughput through Parallel Execution Using Tensor Cores and CUDA CoresKhoa Ho, Hui Zhao 0013, Adwait Jog, Saraju P. Mohanty. 223-228 [doi]
- CosMos: Building A Network Reliability Cost Modeling System for Customer SLAManasa Leela Gummadavelly, Haymanot Gebre-Amlak, Henry Zhu, Sejun Song, Baek-Young Choi. 229-234 [doi]
- Adiabatic Logic-based STT-MRAM Design for IoTWu Yang, Amit Degada, Himanshu Thapliyal. 235-240 [doi]
- Robust Perception Architecture Design for Automotive Cyber-Physical SystemsJoydeep Dey, Sudeep Pasricha. 241-246 [doi]
- Secure and Scalable Collaborative Edge Computing using Decision TreeDeepak Puthal, Ernesto Damiani, Saraju P. Mohanty. 247-252 [doi]
- Predicting GPU Performance and System Parameter Configuration Using Machine LearningZhuren Liu, Trevor Exley, Austin Meek, Rachel Yang, Hui Zhao, Mark V. Albert. 253-258 [doi]
- The Road to Widely Deploying Processing-in-Memory: Challenges and OpportunitiesSaugata Ghose. 259-260 [doi]
- Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric ArchitecturesGeraldo F. Oliveira, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu. 261-266 [doi]
- PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM TechniquesAtaberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami 0001, Hasan Hassan, Oguz Ergin, Onur Mutlu. 267-272 [doi]
- Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and DatabasesGeraldo F. Oliveira, Amirali Boroumand, Saugata Ghose, Juan Gómez-Luna, Onur Mutlu. 273-278 [doi]
- Exploiting Near-Data Processing to Accelerate Time Series AnalysisIvan Fernandez, Ricardo Quislant, Christina Giannoula, Mohammed Alser, Juan Gómez-Luna, Eladio Gutiérrez, Oscar G. Plata, Onur Mutlu. 279-282 [doi]
- GenStore: In-Storage Filtering of Genomic Data for High-Performance and Energy-Efficient Genome AnalysisNika Mansouri-Ghiasi, Jisung Park 0001, Harun Mustafa, Jeremie S. Kim, Ataberk Olgun, Arvid Gollwitzer, Damla Senol Cali, Can Firtina, Haiyu Mao, Nour Almadhoun Alserr, Rachata Ausavarungnirun, Nandita Vijaykumar, Mohammed Alser, Onur Mutlu. 283-287 [doi]
- SparseP: Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory ArchitecturesChristina Giannoula, Ivan Fernandez, Juan Gómez-Luna, Nectarios Koziris, Georgios I. Goumas, Onur Mutlu. 288-291 [doi]
- Machine Learning Training on a Real Processing-in-Memory SystemJuan Gómez-Luria, Yuxin Guo, Sylvan Brocard, Julien Legriel, Remy Cimadomo, Geraldo F. Oliveira, Gagandeep Singh 0002, Onur Mutlu. 292-295 [doi]
- WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing SystemsJiangwei Zhang, Chong Wang, Yi Cai 0003, Zhenhua Zhu, Donald Kline, Huazhong Yang, Yu Wang. 296-301 [doi]
- A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory AcceleratorsJames Read, Wantong Li, Shimeng Yu. 302-307 [doi]
- SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D ArchitectureNikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel 0001, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar 0001, Johann Knechtel, Ozgur Sinanoglu. 308-313 [doi]
- Security as an Important Ingredient in Neuromorphic EngineeringFarhad Merchant. 314-319 [doi]
- A DNN Protection Solution for PIM accelerators with Model CompressionLei Zhao, Youtao Zhang, Jun Yang 0002. 320-325 [doi]
- Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural NetworksAlberto Bosio, Bastien Deveautour, Ian O'Connor. 326 [doi]
- Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUsFernando dos Santos, Paolo Rech, Angeliki Kritikakou, Olivier Sentieys. 327 [doi]
- Energy-aware Adaptive Approximate Computing for Deep Learning ApplicationsNima Taherinejad, Salar Shakibhamedan. 328 [doi]
- Fault Resilience of DNN Accelerators for Compressed Sensor InputsAyush Arunachalam, Shamik Kundu, Arnab Rahat, Suvadeep Banerjee, Kanad Basu. 329-332 [doi]
- Probabilistic Fault Grading for AI Accelerators using Neural TwinsArjun Chaudhuri, Jonti Talukdar, Krishnendu Chakrabarty. 333-338 [doi]
- Towards Yield Improvement for AI Accelerators: Analysis and ExplorationMohammad Walid Charrwi, Huy Phan, Bo Yuan 0001, Samah Mohamed Saeed. 339-344 [doi]
- Exploring Image Selection for Self-Testing in Neural Network AcceleratorsFanruo Meng, Chengmo Yang. 345-350 [doi]
- Towards Independent On-device Artificial IntelligenceYawen Wu, Jingtong Hu. 351 [doi]
- Hardware-aware Automated Architecture Search for Brain-inspired Hyperdimensional ComputingJunhuan Yang, Venkat Kalyan Reddy Yasa, Yi-sheng, Dayane Reis, Xun Jiao, Weiwen Jiang, Lei Yang. 352-357 [doi]
- Hardware/Software Co-Exploration for Graph Neural Architectures on FPGAsQing Lu, Weiwen Jiang, Meng Jiang, Jingtong Hu, Yiyu Shi. 358-362 [doi]
- A Novel Marketplace Perspective Promoting Customized Low Energy Computing and IoT: The SMART4ALL ApproachEvanthia Faliagka, Christos Panagiotou, Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros. 363-368 [doi]
- Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDARTobias Dörr, Florian Schade, Leonard Masing, Jürgen Becker 0001, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Vasilios I. Kelefouras, Nikolaos S. Voros. 369-370 [doi]
- Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGATim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker 0001, Imen Baili. 371-372 [doi]
- Efficient Autonomous Driving System Design: From Software to HardwareYu Wang 0002, Shulin Zeng, Kaiyuan Guo, Xuefei Ning, Yali Zhao, Zhongyuan Qiu, Changcheng Tang, Shuang Liang, Huazhong Yang. 373-375 [doi]
- Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian RhythmsMuhammed Ceylan Morgül, Xinfei Guo, Mircea Stan. 376-379 [doi]
- Hardware Emulation of FeFET On FPGAPaul-Antoine Matrangolo, Cédric Marchand 0002, David Navarro, Ian O'Connor. 380-385 [doi]
- Secure PUF-based Authentication and Key Exchange Protocol using Machine LearningAmir Ali Pour, Fatemeh Afghah, David Hély, Vincent Beroulle, Giorgio Di Natale. 386-389 [doi]
- Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural NetworksTaisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi. 390-393 [doi]
- REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architectureRaghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh. 394-397 [doi]
- On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore ClusterMichael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini. 398-401 [doi]
- Exact Mapping of Quantum Circuit Partitions to Building Blocks of the SAQIP ArchitectureAmirmohammad Biuki, Naser MohammadZadeh, Robert Wille, Sahar Sargaran. 402-405 [doi]
- Possible Reductions to Generate circuits from BDDsEduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis. 406-409 [doi]
- Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit MethodBinjing Li, Siyuan Lu, Keli Xie, Zhongfeng Wang. 410-413 [doi]
- A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing ApplicationsMd. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury. 414-417 [doi]
- A Permutation Challenge Input Interface for Arbiter PUF Variants Against Machine Learning AttacksYu Zhuang, Gaoxiang Li, Khalid T. Mursi. 418-421 [doi]
- Accuracy Configurable FPGA Implementation of Harris Corner DetectionShivani Maurya, Ziaul Choudhury, Suresh Purini. 422-427 [doi]
- Designing Data-Aware Network-on-Chip for PerformanceAbhijit Das 0002, John Jose. 428-433 [doi]
- On the Detection and Circumvention of Bitstream-level Trojans in FPGAsQazi Arbab Ahmed, Marco Platzner. 434-439 [doi]
- Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant ApplicationsHaroon Waris, Chenghua Wang, Weiqiang Liu. 440-445 [doi]
- Securing hard drives with the Security Protocol and Data Model (SPDM)Renan C. A. Alves, Bruno C. Albertini, Marcos A. Simplício Jr.. 446-447 [doi]
- Fall-Sense: An Enhanced Sensor System to Predict and Detect Elderly Falls using IoMTLaavanya Rachakonda, Daniel T. Marchand. 448-449 [doi]
- A Novel Approach to Quantum Circuit PartitioningJoseph Clark, Himanshu Thapliyal, Travis S. Humble. 450-451 [doi]
- MC- PUF: A Robust Lightweight Controlled Physical Unclonable Function for Resource Constrained EnvironmentsPintu Kumar Sadhu, Venkata P. Yanambaka. 452-453 [doi]