P5: Programmable Parsers with Packet-level Parallel Processing for FPGA-based Switches

Junnan Li, ZhiGang Sun, Biao Han. P5: Programmable Parsers with Packet-level Parallel Processing for FPGA-based Switches. In ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2017, Beijing, China, May 18-19, 2017. pages 107-108, IEEE, 2017. [doi]

Abstract

Abstract is missing.