Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks. Process Variation Tolerant 3T1D-Based Cache Architectures. In 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA. pages 15-26, IEEE Computer Society, 2007. [doi]
@inproceedings{LiangCWB07,
title = {Process Variation Tolerant 3T1D-Based Cache Architectures},
author = {Xiaoyao Liang and Ramon Canal and Gu-Yeon Wei and David Brooks},
year = {2007},
doi = {10.1109/MICRO.2007.33},
url = {http://doi.ieeecomputersociety.org/10.1109/MICRO.2007.33},
tags = {caching, architecture},
researchr = {https://researchr.org/publication/LiangCWB07},
cites = {0},
citedby = {0},
pages = {15-26},
booktitle = {40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA},
publisher = {IEEE Computer Society},
}