Abstract is missing.
- Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi. 3-14 [doi]
- Process Variation Tolerant 3T1D-Based Cache ArchitecturesXiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks. 15-26 [doi]
- Mitigating Parameter Variation with Dynamic Fine-Grain Body BiasingRadu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas. 27-42 [doi]
- Optimal versus Heuristic Global Code SchedulingSebastian Winkel. 43-55 [doi]
- Global Multi-Threaded Instruction SchedulingGuilherme Ottoni, David I. August. 56-68 [doi]
- Revisiting the Sequential Programming Model for Multi-CoreMatthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas Jablin, David I. August. 69-84 [doi]
- Penelope: The NBTI-Aware ProcessorJaume Abella, Xavier Vera, Antonio González. 85-96 [doi]
- Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and EvaluationKypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco. 97-108 [doi]
- Self-calibrating Online Wearout DetectionJason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke. 109-122 [doi]
- Implementing Signatures for Transactional MemoryDaniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam. 123-133 [doi]
- Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMsMrinmoy Ghosh, Hsien-Hsin S. Lee. 134-145 [doi]
- Stall-Time Fair Memory Access Scheduling for Chip MultiprocessorsOnur Mutlu, Thomas Moscibroda. 146-160 [doi]
- Impact of Cache Coherence Protocols on the Processing of Network TrafficAmit Kumar, Ram Huggahalli. 161-171 [doi]
- Flattened Butterfly Topology for On-Chip NetworksJohn Kim, James D. Balfour, William J. Dally. 172-182 [doi]
- Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-FriendlyBrian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin. 183-196 [doi]
- Multi-bit Error Tolerant Caches Using Two-Dimensional Error CodingJangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe. 197-209 [doi]
- Argus: Low-Cost, Comprehensive Error Detection in Simple CoresAlbert Meixner, Michael E. Bauer, Daniel J. Sorin. 210-222 [doi]
- Leveraging 3D Technology for Improved ReliabilityNiti Madan, Rajeev Balasubramonian. 223-235 [doi]
- Effective Optimistic-Checker Tandem Core Design through Architectural PruningFrancisco J. Mesa-Martinez, Jose Renau. 236-248 [doi]
- FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate SimulatorsDerek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat. 249-261 [doi]
- Microarchitectural Design Space Exploration Using an Architecture-Centric ApproachChristophe Dubach, Timothy M. Jones, Michael F. P. O Boyle. 262-271 [doi]
- Informed Microarchitecture Design Space Exploration Using Workload DynamicsChang-Burm Cho, Wangyuan Zhang, Tao Li. 274-285 [doi]
- Time Interpolation: So Many Metrics, So Few RegistersTodd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan. 286-300 [doi]
- Low-Cost Epoch-Based Correlation Prefetching for Commercial ApplicationsYuan Chou. 301-313 [doi]
- A Framework for Coarse-Grain Optimizations in the On-Chip Memory HierarchyJason Zebchuk, Elham Safi, Andreas Moshovos. 314-327 [doi]
- Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring MultiprocessorsKarin Strauss, Xiaowei Shen, Josep Torrellas. 327-342 [doi]
- A Framework for Providing Quality of Service in Chip Multi-ProcessorsFei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer. 343-355 [doi]
- A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C ProgramsWilliam Thies, Vikram Chandrasekhar, Saman P. Amarasinghe. 356-369 [doi]
- Data Access Partitioning for Fine-grain Parallelism on Multicore ArchitecturesMichael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke. 369-380 [doi]
- Composable Lightweight ProcessorsChangkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler. 381-394 [doi]
- The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics AccelerationThomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, Glenn Reinman. 394-406 [doi]
- Dynamic Warp Formation and Scheduling for Efficient GPU Control FlowWilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt. 407-420 [doi]
- Scavenger: A New Last Level Cache Architecture with Global Block PriorityArkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez. 421-432 [doi]
- Guaranteeing Hits to Improve the Efficiency of a Small Instruction CacheStephen Hines, David B. Whalley, Gary S. Tyson. 433-444 [doi]
- Emulating Optimal Replacement with a Shepherd CacheKaushik Rajan, Govindarajan Ramaswamy. 445-454 [doi]