Yun Liang, Tulika Mitra, Lei Ju. Instruction Cache Locking Using Temporal Reuse Profile. IEEE Trans. on CAD of Integrated Circuits and Systems, 34(9):1387-1400, 2015. [doi]
@article{LiangMJ15,
title = {Instruction Cache Locking Using Temporal Reuse Profile},
author = {Yun Liang and Tulika Mitra and Lei Ju},
year = {2015},
doi = {10.1109/TCAD.2015.2418320},
url = {http://dx.doi.org/10.1109/TCAD.2015.2418320},
researchr = {https://researchr.org/publication/LiangMJ15},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {34},
number = {9},
pages = {1387-1400},
}