A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area

Qing Liao 0005, Shuguo Li. A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area. In ICDSP 2020: 4th International Conference on Digital Signal Processing, Chengdu, China, June 19-21, 2020. pages 284-288, ACM, 2020. [doi]

Abstract

Abstract is missing.