A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters - researchr publication authors

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Rong Lin. A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters. In 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings. pages 182, IEEE Computer Society, 2003. [doi]

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