Design technology challenges for system and chip level designs in very deep submicron technologies

James Lin. Design technology challenges for system and chip level designs in very deep submicron technologies. In Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou, editors, Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003. pages 194, ACM, 2003. [doi]

@inproceedings{Lin03,
  title = {Design technology challenges for system and chip level designs in very deep submicron technologies},
  author = {James Lin},
  year = {2003},
  doi = {10.1145/944645.944695},
  url = {http://doi.acm.org/10.1145/944645.944695},
  tags = {design},
  researchr = {https://researchr.org/publication/Lin03},
  cites = {0},
  citedby = {0},
  pages = {194},
  booktitle = {Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003},
  editor = {Rajesh Gupta and Yukihiro Nakamura and Alex Orailoglu and Pai H. Chou},
  publisher = {ACM},
  isbn = {1-58113-742-7},
}