Table of Contents

• Virtual synchronization technique with OS modeling for fast and time-accurate cosimulationYoungmin Yi, Dohyung Kim, Soonhoi Ha. 1-6 [doi]
• A modular simulation framework for architectural exploration of on-chip interconnection networksTim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens. 7-12 [doi]
• An efficient retargetable framework for instruction-set simulationMehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt. 13-18 [doi]
• Transaction level modeling: an overviewLukai Cai, Daniel Gajski. 19-24 [doi]
• Extending the SystemC synthesis subset by object-oriented featuresEike Grimpe, Frank Oppenheimer. 25-30 [doi]
• RTOS scheduling in transaction level modelsHaobo Yu, Andreas Gerstlauer, Daniel Gajski. 31-36 [doi]
• Synthesizing operating system based device drivers in embedded systemsShaojie Wang, Sharad Malik. 37-44 [doi]
• Hardware support for real-time operating systemsPaul Kohout, Brinda Ganesh, Bruce L. Jacob. 45-51 [doi]
• Programming embedded networked sensor systemsFeng Zhao, Jie Liu, Jim Reich, Maurice Chu, Juan Liu. 52 [doi]
• Design space exploration of a hardware-software co-designed GF(2:::m:::) galois field processor for forward error correction and cryptographyWei Ming Lim, Mohammed Benaissa. 53-58 [doi]
• A fast parallel reed-solomon decoder on a reconfigurable architectureArezou Koohi, Nader Bagherzadeh, Chengzi Pan. 59-64 [doi]
• The analysis and design of architecture systems for speech recognition on modern handheld-computing devicesAndreas Hagen, Daniel A. Connors, Bryan L. Pellom. 65-70 [doi]
• Industry best practices in embedded softwareRaul Camposano, Mark Underseth, Faraydon Karim. 72-73 [doi]
• Architectural versus physical solutions for on-chip communication challengesDoug Burger. 74 [doi]
• On-chip communication design: roadblocks and avenuesLuca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 75-76 [doi]
• Architecture and synthesis for multi-cycle on-chip communicationJason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang. 77-78 [doi]
• System-level design tools: who needs them, who has them, and how much should they cost?Reinaldo A. Bergamaschi, Grant Martin. 79-80 [doi]
• Driving forces behind SOC developmentMojy C. Chian. 81 [doi]
• Driving agenda for systems researchNik Dutt, Janos Sztipanovits, Masaki Hirata. 82 [doi]
• Design optimization of mixed time/event-triggered distributed embedded systemsTraian Pop, Petru Eles, Zebo Peng. 83-89 [doi]
• Deriving process networks from weakly dynamic applications in system-level designTodor Stefanov, Ed F. Deprettere. 90-96 [doi]
• A low-cost and low-power multi-standard video encoderRafael Peset Llopis, Ramanathan Sethuraman, Carlos A. Alba Pinto, Harm Peters, Steffen Maul, Marcel Oosterhuis. 97-102 [doi]
• A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP coreBehzad Mohebbi, Eliseu Chavez Filho, Rafael Maestre, Mark Davies, Fadi J. Kurdahi. 103-108 [doi]
• A codesigned on-chip logic minimizerRoman L. Lysecky, Frank Vahid. 109-113 [doi]
• Synthesis of real-time embedded software with local and global deadlinesPao-Ann Hsiung, Cheng-Yi Lin. 114-119 [doi]
• Pareto-optimization-based run-time task scheduling for embedded systemsPeng Yang, Francky Catthoor. 120-125 [doi]
• A low power scheduler using game theoryN. Ranganathan, Ashok K. Murugavel. 126-131 [doi]
• VL-CDRAM: variable line sized cached DRAMsAnanth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 132-137 [doi]
• A low-cost memory architecture with NAND XIP for mobile embedded systemsChanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, Shinhan Kim, Bumsoo Kim. 138-143 [doi]
• Design space minimization with timing and code size optimization for embedded DSPQingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha. 144-149 [doi]
• SEAS: a system for early analysis of SoCsReinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal. 150-155 [doi]
• Programmers views of SoCsJoAnn M. Paul. 156-181 [doi]
• Security wrappers and power analysis for SoC technologiesCatherine H. Gebotys, Y. Zhang. 162-167 [doi]
• First results with eBlocks: embedded systems building blocksSusan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh. 168-175 [doi]
• Verification of design decisions in ForSyDeTarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Axel Jantsch. 176-181 [doi]
• A multiobjective optimization model for exploring multiprocessor mappings of process networksCagkan Erbas, Selin C. Erbas, Andy D. Pimentel. 182-187 [doi]
• A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chipHeiko Zimmer, Axel Jantsch. 188-193 [doi]
• Design technology challenges for system and chip level designs in very deep submicron technologiesJames Lin. 194 [doi]
• Schedule-aware performance estimation of communication architecture for efficient design space explorationSungchan Kim, Chaeseok Im, Soonhoi Ha. 195-200 [doi]
• Accurate estimation of cache-related preemption delayHemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury. 201-206 [doi]
• Early estimation of the size of VHDL projectsWilliam Fornaciari, Fabio Salice, Daniele Paolo Scarpazza. 207-212 [doi]
• Tracking object life cycle for leakage energy optimizationGuangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko. 213-218 [doi]
• Compiler parallelization of C programs for multi-core DSPs with multiple address spacesBjörn Franke, Michael F. P. O Boyle. 219-224 [doi]
• Architectural analysis and instruction-set optimization for design of network protocol processorsHaiyong Xie, Li Zhao, Laxmi N. Bhuyan. 225-230 [doi]
• The future of system-level design: can we find the right solutions to the right problems at the right time?Reinaldo A. Bergamaschi, Grant Martin, Wayne Wolf, Rolf Ernst, Kees A. Vissers, Jack Kouloheris. 231 [doi]