The following publications are possibly variants of this publication:
- Z4: A New Depth-Size Optimal Parallel Prefix Circuit With Small DepthYen-Chun Lin, Jian-Nan Chen. npsc, 11:221-236, 2003.
- A New Class of Depth-Size Optimal Parallel Prefix CircuitsYen-Chun Lin, Chao-Cheng Shih. tjs, 14(1):39-52, 1999. [doi]
- Constructing ::::H::::4, a Fast Depth-Size Optimal Parallel Prefix CircuitYen-Chun Lin, Yao-Hsien Hsu, Chun-Keng Liu. tjs, 24(3):279-304, 2003. [doi]
- A new class of depth-size optimal parallel prefix circuitsYen-Chun Lin, Chao-Cheng Shih. cata 1998: 117-120
- Fast problem-size-independent parallel prefix circuitsYen-Chun Lin, Li-Ling Hung. jpdc, 69(4):382-388, 2009. [doi]
- Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2Yen-Chun Lin, Li-Ling Hung. todaes, 14(1), 2009. [doi]
- A new approach to constructing optimal parallel prefix circuits with small depthYen-Chun Lin, Jun-Wei Hsiao. jpdc, 64(1):97-107, 2004. [doi]