The following publications are possibly variants of this publication:
- A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist BandwidthTsung-Chih Hung, Tai-Haur Kuo. cicc 2019: 1-4 [doi]
- A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architectureSang Min Lee, Dongwon Seo, Shahin Mehdizad Taleie, Derui Kong, Michael Joseph McGowan, Tongyu Song, Ganesh R. Saripalli, Jenny Kuo, Seyfi S. Bazarjani. vlsic 2015: 164 [doi]
- A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist ZoneHung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo. jssc, 56(10):3145-3156, 2021. [doi]