Jing Lin, Xiaola Lin. Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network. The Journal of Supercomputing, 61(3):1048-1067, 2012. [doi]
@article{LinL12-13,
title = {Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network},
author = {Jing Lin and Xiaola Lin},
year = {2012},
doi = {10.1007/s11227-011-0676-3},
url = {http://dx.doi.org/10.1007/s11227-011-0676-3},
researchr = {https://researchr.org/publication/LinL12-13},
cites = {0},
citedby = {0},
journal = {The Journal of Supercomputing},
volume = {61},
number = {3},
pages = {1048-1067},
}