Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs - researchr publication

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Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai. Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. ACM Trans. Design Autom. Electr. Syst., 17(3):34, 2012. [doi]

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