Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li. Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. pages 437-442, IEEE, 2012. [doi]
Abstract is missing.