A multiple code-rate turbo decoder based on reciprocal dual trellis architecture

Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang. A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 1496-1499, IEEE, 2010. [doi]

Authors

Chen-Yang Lin

This author has not been identified. Look up 'Chen-Yang Lin' in Google

Cheng-Chi Wong

This author has not been identified. Look up 'Cheng-Chi Wong' in Google

Hsie-Chia Chang

This author has not been identified. Look up 'Hsie-Chia Chang' in Google