An FPGA-Efficient CNN Accelerator for Hybrid Model Compression With Scalable Bit-Serial and Bit-Parallel MAC

Yuanmiao Lin, Zijian Zhang, Xueming Li 0001, Hongmin Huang, Heng Mai, Ruidian Zhan, Xianghong Hu 0001, Shuting Cai, Xiaoming Xiong. An FPGA-Efficient CNN Accelerator for Hybrid Model Compression With Scalable Bit-Serial and Bit-Parallel MAC. IEEE Trans. Circuits Syst. I Regul. Pap., 73(8):5528-5541, August 2026. [doi]

Abstract

Abstract is missing.