Yu-Yee Liow, Chung-Yu Wu. The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques. In ISCAS (4). pages 117-120, 2002. [doi]
@inproceedings{LiowW02,
title = {The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques},
author = {Yu-Yee Liow and Chung-Yu Wu},
year = {2002},
doi = {10.1109/ISCAS.2002.1010174},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2002.1010174},
tags = {design},
researchr = {https://researchr.org/publication/LiowW02},
cites = {0},
citedby = {0},
pages = {117-120},
booktitle = {ISCAS (4)},
}