Joseph Lis, Daniel Gajski. VHDL Synthesis Using Structured Modeling. In DAC. pages 606-609, 1989. [doi]
@inproceedings{LisG89,
title = {VHDL Synthesis Using Structured Modeling},
author = {Joseph Lis and Daniel Gajski},
year = {1989},
doi = {10.1145/74382.74486},
url = {http://doi.acm.org/10.1145/74382.74486},
tags = {modeling},
researchr = {https://researchr.org/publication/LisG89},
cites = {0},
citedby = {0},
pages = {606-609},
booktitle = {DAC},
}