Scott Little, David Walter, Kevin Jones, Chris J. Myers. Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. In Kedar S. Namjoshi, Tomohiro Yoneda, Teruo Higashino, Yoshio Okamura, editors, Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings. Volume 4762 of Lecture Notes in Computer Science, pages 114-128, Springer, 2007. [doi]
Abstract is missing.