Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev. Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 126-131, IEEE Computer Society, 2005. [doi]
Abstract is missing.