Hardware Tripartite Synapse Architecture based on Stochastic Computing

Junxiu Liu, Zhewei Liang, Yuling Luo, Jiadong Huang, Su Yang. Hardware Tripartite Synapse Architecture based on Stochastic Computing. In Dominique Méry, Shengchao Qin, editors, 2019 International Symposium on Theoretical Aspects of Software Engineering, TASE 2019, Guilin, China, July 29-31, 2019. pages 81-85, IEEE, 2019. [doi]

Authors

Junxiu Liu

This author has not been identified. Look up 'Junxiu Liu' in Google

Zhewei Liang

This author has not been identified. Look up 'Zhewei Liang' in Google

Yuling Luo

This author has not been identified. Look up 'Yuling Luo' in Google

Jiadong Huang

This author has not been identified. Look up 'Jiadong Huang' in Google

Su Yang

This author has not been identified. Look up 'Su Yang' in Google