Junxiu Liu, Zhewei Liang, Yuling Luo, Jiadong Huang, Su Yang. Hardware Tripartite Synapse Architecture based on Stochastic Computing. In Dominique Méry, Shengchao Qin, editors, 2019 International Symposium on Theoretical Aspects of Software Engineering, TASE 2019, Guilin, China, July 29-31, 2019. pages 81-85, IEEE, 2019. [doi]
@inproceedings{LiuLLHY19,
title = {Hardware Tripartite Synapse Architecture based on Stochastic Computing},
author = {Junxiu Liu and Zhewei Liang and Yuling Luo and Jiadong Huang and Su Yang},
year = {2019},
doi = {10.1109/TASE.2019.00-16},
url = {https://doi.org/10.1109/TASE.2019.00-16},
researchr = {https://researchr.org/publication/LiuLLHY19},
cites = {0},
citedby = {0},
pages = {81-85},
booktitle = {2019 International Symposium on Theoretical Aspects of Software Engineering, TASE 2019, Guilin, China, July 29-31, 2019},
editor = {Dominique Méry and Shengchao Qin},
publisher = {IEEE},
isbn = {978-1-7281-3342-3},
}