Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses

Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra. Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA. pages 17-24, IEEE, 2006. [doi]

@inproceedings{LiuSM06:1,
  title = {Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses},
  author = {Jiangjiang Liu and Krishnan Sundaresan and Nihar R. Mahapatra},
  year = {2006},
  url = {http://www.iccd-conference.org/proceedings/2006/paper_228.pdf},
  tags = {optimization},
  researchr = {https://researchr.org/publication/LiuSM06%3A1},
  cites = {0},
  citedby = {0},
  pages = {17-24},
  booktitle = {24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA},
  publisher = {IEEE},
}