Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses

Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra. Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. In 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA. pages 17-24, IEEE, 2006. [doi]

Abstract

Abstract is missing.