A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada. A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. J. Solid-State Circuits, 53(12):3672-3687, 2018. [doi]

@article{LiuSTHKCDWO18,
  title = {A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS},
  author = {Hanli Liu and Zheng Sun and Dexian Tang and Hongye Huang and Tohru Kaneko and Zhijie Chen and Wei Deng and Rui Wu and Kenichi Okada},
  year = {2018},
  doi = {10.1109/JSSC.2018.2878822},
  url = {https://doi.org/10.1109/JSSC.2018.2878822},
  researchr = {https://researchr.org/publication/LiuSTHKCDWO18},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {53},
  number = {12},
  pages = {3672-3687},
}