A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation

Ye Liu, Yin Wang, Liang Chang 0002, Jun Zhou 0017. A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation. In 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020, Nanjing, China, November 23-25, 2020. pages 61-62, IEEE, 2020. [doi]

@inproceedings{LiuW0020,
  title = {A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation},
  author = {Ye Liu and Yin Wang and Liang Chang 0002 and Jun Zhou 0017},
  year = {2020},
  doi = {10.1109/ICTA50426.2020.9331957},
  url = {https://doi.org/10.1109/ICTA50426.2020.9331957},
  researchr = {https://researchr.org/publication/LiuW0020},
  cites = {0},
  citedby = {0},
  pages = {61-62},
  booktitle = {2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020, Nanjing, China, November 23-25, 2020},
  publisher = {IEEE},
  isbn = {978-1-7281-8032-8},
}