VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM) - researchr publication

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Siu Hong Loh, You Hong Liew, Jia-Jia Sim. VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM). In 12th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2022, Penang, Malaysia, October 21-22, 2022. pages 7-12, IEEE, 2022. [doi]

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