Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton. Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. In Malay K. Ganai, Armin Biere, editors, Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, Austin, USA, November 3, 2011. Volume 832 of CEUR Workshop Proceedings, CEUR-WS.org, 2011. [doi]
Abstract is missing.