Andreas Lööw. Lutsig: a verified Verilog compiler for verified circuit development. In Catalin Hritcu, Andrei Popescu 0001, editors, CPP '21: 10th ACM SIGPLAN International Conference on Certified Programs and Proofs, Virtual Event, Denmark, January 17-19, 2021. pages 46-60, ACM, 2021. [doi]
Abstract is missing.