High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS

Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesús Gutiérrez 0004, Milos Krstic, Eckhard Grass. High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS. In 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022. pages 1-6, IEEE, 2022. [doi]

@inproceedings{LopacinskiHPMGK22,
  title = {High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS},
  author = {Lukasz Lopacinski and Alireza Hasani and Goran Panic and Nebojsa Maletic and Jesús Gutiérrez 0004 and Milos Krstic and Eckhard Grass},
  year = {2022},
  doi = {10.1109/VLSI-SoC54400.2022.9939603},
  url = {https://doi.org/10.1109/VLSI-SoC54400.2022.9939603},
  researchr = {https://researchr.org/publication/LopacinskiHPMGK22},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022},
  publisher = {IEEE},
  isbn = {978-1-6654-9005-4},
}