Table of Contents

• SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage PartitionYidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang. 1-6 [doi]
• Exploring Approximate Computing Approaches to Design Power-efficient MultipliersVinicius Zanandrea, Cristina Meinhardt. 1-2 [doi]
• 30 GHz Front-End with Adaptively Biased PA and Current Steering LNA for Phased Array SystemsPanagiotis Gkoutis, Georgios Konidas, Grigorios Kalivas. 1-6 [doi]
• Towards Energy Efficient DNN accelerator via Sparsified Gradual Knowledge DistillationForoozan Karimzadeh, Arijit Raychowdhury. 1-6 [doi]
• Substrate Effect on Low-frequency Noise of synaptic RRAM devicesNikolaos Vasileiadis, Alexandros Mavropoulis, Panagiotis Loukas, Pascal Normand, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis. 1-5 [doi]
• Stitch-avoiding Detailed Routing for Multiple E-Beam LithographyKritanta Saha, Pritha Banerjee, Susmita Sur-Kolay. 1-6 [doi]
• A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technologyManasa Madhvaraj, Salvador Mir, Manuel J. Barragan. 1-6 [doi]
• RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoCAkshay Sarman, Alwin Shaju, Rose George Kunthara, K. Neethu, Rekha K. James, John Jose. 1-6 [doi]
• Power Analysis Attack on Locking SIB based IJTAG AchitectureGaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat. 1-6 [doi]
• Toward Large Scale All-Optical Spiking Neural NetworksMilad Eslaminia, Sébastien Le Beux. 1-6 [doi]
• A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCsAlexander Fusco, Md Sahil Hassan, Joshua Mack, Ali Akoglu. 1-6 [doi]
• Routability-Driven Detailed Placement Using Reinforcement LearningSheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt. 1-2 [doi]
• Analog Compute in Memory and Breaking Digital Number RepresentationsNathan Laubeuf. 1-2 [doi]
• Confidential Inference in Decision Trees: FPGA Design and ImplementationRupesh Raj Karn, Ibrahim Abe M. Elfadel. 1-6 [doi]
• System Design for Computation-in-Memory: From Primitive to Complex FunctionsMahdi Zahedi, Taha Shahroodi, Geert Custers, Abhairaj Singh, Stephan Wong, Said Hamdioui. 1-6 [doi]
• Generation of Formal CPU Profiles for Embedded SystemsStian Gerlach Sørensen, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz. 1-6 [doi]
• Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM)Asmae El Arrassi, Anteneh Gebregiorgis, Anass El Haddadi, Said Hamdioui. 1-6 [doi]
• SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite ImagesElissaios-Alexios Papatheofanous, Ph. Tziolos, V. Kalekis, Tz. Amrou, George E. Konstantoulakis, G. Venitourakis, Dionysios I. Reisis. 1-4 [doi]
• Preserving Design Hierarchy Information for Polynomial Formal VerificationRolf Drechsler, Alireza Mahzoon. 1-7 [doi]
• Efficient Dynamic Logic Magnitude ComparatorsConstantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas. 1-5 [doi]
• A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip DesignsAnu Asokan. 1-6 [doi]
• High-Performance Hardware Accelerators for Next Generation On-Board Data ProcessingAntonis M. Paschalis, Panagiotis Chatziantoniou, Dimitris Theodoropoulos, Antonis Tsigkanos, Nektarios Kranitis. 1-4 [doi]
• Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less TransistorsLucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker. 1-2 [doi]
• Accurate real-time UAV flight-mode classificationNikolaos Georgiou, Panayiotis Kolios. 1-6 [doi]
• NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing ToolNils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger 0001. 1-6 [doi]
• Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis FlowsNikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou. 1-6 [doi]
• Exploring Approximate Comparator Circuits on Power Efficient Design of Decision TreesPedro Aquino Silva, Mateus Grellert, Cristina Meinhardt. 1-6 [doi]
• Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) EncoderRenjie Chen, Aaron Stillmaker, Bevan M. Baas. 1-6 [doi]
• Run Time Power and Accuracy Management with Approximate CircuitsNahla A. El-Araby, David Frismuth, Nilson Neves Filho, Axel Jantsch. 1-6 [doi]
• Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level SparsityForoozan Karimzadeh, Arijit Raychowdhury. 1-2 [doi]
• Guiding FPGA Detailed Placement via Reinforcement LearningP. Esmaeili, Timothy Martin, Shawki Areibi, Gary Gréwal. 1-6 [doi]
• Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the EdgeAshwin Bhat, Adou Sangbone Assoa, Arijit Raychowdhury. 1-6 [doi]
• Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressionsSamuele Germiniani, Graziano Pravadelli. 1-6 [doi]
• An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge ComputingMichael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon. 1-6 [doi]
• Approximation Workflow for Energy-Efficient Comparators in Decision Tree ApplicationsPedro Silva, Mateus Grellert, Cristina Meinhardt. 1-2 [doi]
• Embedded TCP/IP Controller for a RISC-V SoCChun-Jen Tsai, Yi-De Lee. 1-6 [doi]
• A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence CheckingRaiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh. 1-6 [doi]
• High-Level Synthesis design approach for Number-Theoretic MultiplierAlexander El-Kady, Apostolos P. Fournaris, Evangelos Haleplidis, Vassilis Paliouras. 1-6 [doi]
• FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth MemoryChristopher Chuvalas, Ranga Vemuri. 1-6 [doi]
• Quantum Computing-Assisted Channel Estimation for Massive MIMO mmWave SystemsEvangelos Vlachos, Kostas Blekos. 1-6 [doi]
• Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional ComputingShubham Kumar, Swetaki Chatterjee, Simon Thomann, Paul R. Genssler, Yogesh Singh Chauhan, Hussam Amrouch. 1-6 [doi]
• A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core PlatformsAndreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros. 1-6 [doi]
• High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite ImagesKonstantina Koliogeorgi, Dimitris Mylonakis, Sotirios Xydis, Dimitrios Soudris. 1-6 [doi]
• Frequency Synthesizers for 5G ApplicationsSalvatore Levantino. 1-4 [doi]
• Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space ApplicationsVasileios Leon, George Lentaris, Dimitrios Soudris, Simon Vellas, Mathieu Bernou. 1-4 [doi]
• An FPGA implementation of the VESA Display Stream Compression decoderNikolaos Kefalas, George Theodoridis. 1-6 [doi]
• RISC-V Processor Trace Encoder with Multiple Instructions Retirement SupportHalil Kükner, Gökhan Kaplayan, Ahmet Efe, Mehmet Ali Gülden. 1-6 [doi]
• Secrecy Spectral Efficiency Optimization in RIS-Enabled MIMO Communication SystemsKonstantinos D. Katsanos, George C. Alexandropoulos. 1-6 [doi]
• Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in SpaceVasileios Leon, Elissaios-Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios I. Reisis, Dimitrios Soudris. 1-6 [doi]
• Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT SystemsKonstantinos Falis, Andreas Tsiougkos, Vasilis F. Pavlidis. 1-6 [doi]
• MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the EdgeTheo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit. 1-6 [doi]
• A Power Reduction Technique Based on Linear Transformations for Block CiphersElif Bilge Kavun. 1-6 [doi]
• Modeling frequency response of gm-boosted inductorless Common-Gate LNAJorge Marqués-García, Alberto Arcusa-Puente, Antonio D. Martínez-Pérez, Francisco Aznar. 1-2 [doi]
• High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOSLukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesús Gutiérrez 0004, Milos Krstic, Eckhard Grass. 1-6 [doi]
• A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAMJose Cayo, Ioannis Vourkas, Antonio Rubio. 1-4 [doi]
• A low-power, radiation-hardened Single Event Effect rate detection System on a Chip for Real Time Monitoring of Single Event Effects on Low Earth Orbit satellitesGeorgios Kottaras, Theodoros Sarris, Athanasios M. Psomoulis, Ilias Ioakeimidis, Angelos Papathanasiou, David Pitchford, Ingmar Sandberg. 1-6 [doi]
• Speculative guardband: exploiting critical-delay variations across cached instructionsJohannes W. Farias, Diego V. Cirilo do Nascimento, Tiago Barros, Samuel Xavier de Souza. 1-2 [doi]
• A Wideband High-Gain Power Amplifier Operating in the D BandVasileios Manouras, Ioannis Papananos. 1-5 [doi]
• Dealing with Non-Idealities in Memristor Based Computation-In-Memory DesignsAnteneh Gebregiorgis, Abhairaj Singh, Sumit Diware, Rajendra Bishnoi, Said Hamdioui. 1-6 [doi]
• A novel wide frequency range 65nm CMOS VCODimitrios Samaras, Andreas Tsimpos, Alkis A. Hatzopoulos. 1-4 [doi]
• Logic Locking of Finite-State Machines Using Transition ObfuscationShahzad Muzaffar, Ibrahim Abe M. Elfadel. 1-6 [doi]
• Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System ModellingRupali Hongekar, Ankita Gupta, Jayakrishna Guddeti, Meghashyam Ashwathnarayan. 1-5 [doi]
• Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit AttacksMohammad Humam Khan, Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi. 1-6 [doi]
• FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech SignalGeorgios Flamis, Stavros Kalapothas, Paris Kitsos. 1-5 [doi]
• Assessing IMD of a Direct-to-RF PlatformJonathan Merk, Changhai Lin, Matthias Kamuf. 1-2 [doi]
• Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose ComputersCan Aknesil, Elena Dubrova. 1-6 [doi]
• Flexible Security and Privacy, System Architecture for IoT, in HealthcareKyriaki Tsantikidou, Nicolas Sklavos 0001. 1-6 [doi]
• LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations ReductionLieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang. 1-6 [doi]
• Architectural Support for Functional ProgrammingCecil Accetti, Peilin Liu. 1-2 [doi]
• A 18-27 GHz Programmable Gain Amplifier in 65-nm CMOS technologyC. del Río Bueno, U. Esteban Eraso, Carlos Sánchez-Azqueta, Santiago Celma. 1-2 [doi]
• Automated Framework for Fast Synthesis of Approximate Hardware AcceleratorsMuhammad Awais 0009, Marco Platzner. 1-2 [doi]
• Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAMCarlos Fernandez, Ioannis Vourkas. 1-6 [doi]
• Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic LoopsNikolaos Chatzivangelis, Dimitris Valiantzas, Christos P. Sotiriou, Iordanis Lilitsis. 1-6 [doi]
• ZaLoBI: Zero avoiding Load Balanced Inference acceleratorImlijungla Longchar, Palash Das, Hemangee K. Kapoor. 1-6 [doi]
• A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock FrequencyBrent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas. 1-5 [doi]
• PA-PUF: A Novel Priority Arbiter PUFSimranjeet Singh, Srinivasu Bodapati, Sachin Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant. 1-6 [doi]
• 2M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and TrackingGourav Datta, Souvik Kundu 0002, Zihan Yin, Joe Mathai, Zeyu Liu, Zixu Wang, Mulin Tian, Shunlin Lu, Ravi Teja Lakkireddy, Andrew Schmidt, Wael Abd-Almageed, Ajey Jacob, Akhilesh R. Jaiswal, Peter A. Beerel. 1-6 [doi]
• Fast and Accurate Model-Driven FPGA-based System-Level Fault EmulationEndri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker. 1-6 [doi]
• FeFET versus DRAM based PIM Architectures: A Comparative StudyChirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn. 1-6 [doi]
• Design and characterisation of a Physically Unclonable Function on FPGA using second-order compensated measurementJ. Fernández-Aragón, Guillermo Díez-Señorans, Miguel Garcia-Bosque, Santiago Celma. 1-2 [doi]
• A CMOS 4-bit Digitally Programmable Phase Shifter for the K-bandU. Esteban Eraso, Carlos Sánchez-Azqueta, Concepción Aldea, Santiago Celma. 1-2 [doi]
• Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error DetectionNicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker. 1-6 [doi]
• End-to-end modeling of variability-aware neural networks based on resistive-switching memory arraysArtem Glukhov, Nicola Lepri, Valerio Milo, Andrea Baroni, Cristian Zambelli, Piero Olivo, Eduardo Pérez, Christian Wenger, Daniele Ielmini. 1-5 [doi]
• Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devicesJonas Gava, Ricardo Reis 0001, Luciano Ost. 1-2 [doi]
• Linear and Periodic State Integrated Circuits Noise Simulation BenchmarkingAnastasios Michailidis, Thomas Noulis, Kostas Siozios. 1-6 [doi]
• Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUsVasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris. 1-2 [doi]
• Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant ApplicationsKamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta 0001, Rolf Drechsler. 1-6 [doi]
• On the Design and Development of a ReRAM-based Computational Memory PrototypeCarlos Fernandez, Ioannis Vourkas. 1-2 [doi]
• ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level CachesYogesh Kumar, S. Sivakumar, John Jose. 1-6 [doi]
• Machine Learning based Power Converter Large Signal Simulation for Energy Harvesting ApplicationsG. Vergos, V. Gogolou, C. Panagiotopoulou, A. Avgoustidis, T. Noulis, Kostas Siozios, S. Siskos. 1-5 [doi]