Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions

J. A. Lopez, G. Domenech, R. Ruiz, Tom J. Kazmierski. Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. In ISCAS (4). pages 77-80, 2002. [doi]

Abstract

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