Clock Network Synthesis with Concurrent Gate Insertion - researchr publication authors

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Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham. Clock Network Synthesis with Concurrent Gate Insertion. In René van Leuken, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers. Volume 6448 of Lecture Notes in Computer Science, pages 228-237, Springer, 2010. [doi]

This author has not been identified. Look up 'Jingwei Lu' in GoogleThis author has not been identified. Look up 'Wing-Kai Chow' in GoogleThis author has not been identified. Look up 'Chiu-Wing Sham' in Google

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