Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham. Clock Network Synthesis with Concurrent Gate Insertion. In René van Leuken, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers. Volume 6448 of Lecture Notes in Computer Science, pages 228-237, Springer, 2010. [doi]
@inproceedings{LuCS10,
title = {Clock Network Synthesis with Concurrent Gate Insertion},
author = {Jingwei Lu and Wing-Kai Chow and Chiu-Wing Sham},
year = {2010},
doi = {10.1007/978-3-642-17752-1_23},
url = {http://dx.doi.org/10.1007/978-3-642-17752-1_23},
researchr = {https://researchr.org/publication/LuCS10},
cites = {0},
citedby = {0},
pages = {228-237},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers},
editor = {René van Leuken and Gilles Sicard},
volume = {6448},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-17751-4},
}