An efficient VLSI architecture of parallel bit plane encoder based on CCSDS IDC - researchr publication related

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Yi Lu, Jie Lei, Yunsong Li. An efficient VLSI architecture of parallel bit plane encoder based on CCSDS IDC. In Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012. pages 1-4, IEEE, 2012. [doi]

The following publications are possibly variants of this publication:

Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of TrinomialsYin Li, Yu Zhang, Xiaoli Guo. vlsi, 2018, 2018. [doi]

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