An efficient VLSI architecture of parallel bit plane encoder based on CCSDS IDC

Yi Lu, Jie Lei, Yunsong Li. An efficient VLSI architecture of parallel bit plane encoder based on CCSDS IDC. In Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012. pages 1-4, IEEE, 2012. [doi]

Abstract

Abstract is missing.