Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu. A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. In Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015. pages 186, IEEE, 2015. [doi]
Abstract is missing.