Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. In Nadine Azémard, Lars J. Svensson, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings. Volume 4644 of Lecture Notes in Computer Science, pages 160-170, Springer, 2007. [doi]
@inproceedings{LuoWHLYX07:0,
title = {A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect},
author = {Hong Luo and Yu Wang and Ku He and Rong Luo and Huazhong Yang and Yuan Xie},
year = {2007},
doi = {10.1007/978-3-540-74442-9_16},
url = {http://dx.doi.org/10.1007/978-3-540-74442-9_16},
researchr = {https://researchr.org/publication/LuoWHLYX07%3A0},
cites = {0},
citedby = {0},
pages = {160-170},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings},
editor = {Nadine Azémard and Lars J. Svensson},
volume = {4644},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-540-74441-2},
}