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Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers

Fei Lyu 0002, Xiaoqi Xu, Yu Wang, Yuanyong Luo, Yuxuan Wang, Hongbing Pan. Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers. IEEE Trans. Circuits Syst. I Regul. Pap., 68(2):715-727, 2021. [doi]

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Fei Lyu 0002

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Xiaoqi Xu

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Yu Wang

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Yuanyong Luo

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Yuxuan Wang

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Hongbing Pan

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