Fei Lyu 0002, Xiaoqi Xu, Yu Wang, Yuanyong Luo, Yuxuan Wang, Hongbing Pan. Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers. IEEE Trans. Circuits Syst. I Regul. Pap., 68(2):715-727, 2021. [doi]
@article{LyuXWLWP21,
title = {Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers},
author = {Fei Lyu 0002 and Xiaoqi Xu and Yu Wang and Yuanyong Luo and Yuxuan Wang and Hongbing Pan},
year = {2021},
doi = {10.1109/TCSI.2020.3038417},
url = {https://doi.org/10.1109/TCSI.2020.3038417},
researchr = {https://researchr.org/publication/LyuXWLWP21},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. I Regul. Pap.},
volume = {68},
number = {2},
pages = {715-727},
}