Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process

Fei Ma, Yan Han, Bo Song, Shurong Dong, Meng Miao, Jianfeng Zheng, Jian Wu, Kehan Zhu. Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process. Microelectronics Reliability, 51(12):2124-2128, 2011. [doi]

Abstract

Abstract is missing.