Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula. Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. In Paolo Ienne, Walid A. Najjar, Jason Anderson, Philip Brisk, Walter Stechele, editors, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. pages 1-8, IEEE, 2016. [doi]
@inproceedings{MaSCSV16,
title = {Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA},
author = {Yufei Ma and Naveen Suda and Yu Cao and Jae-sun Seo and Sarma B. K. Vrudhula},
year = {2016},
doi = {10.1109/FPL.2016.7577356},
url = {http://dx.doi.org/10.1109/FPL.2016.7577356},
researchr = {https://researchr.org/publication/MaSCSV16},
cites = {0},
citedby = {0},
pages = {1-8},
booktitle = {26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016},
editor = {Paolo Ienne and Walid A. Najjar and Jason Anderson and Philip Brisk and Walter Stechele},
publisher = {IEEE},
isbn = {978-2-8399-1844-2},
}